| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 96 === With the shrinking device size in deep submicron process, the process variation influence on circuit performance is more and more serious, especially for analog circuits. Therefore, design-for-manufacturability (DFM) and design-for-yield (DFY) techniques have become popular research directions in recent years. The main concept of DFM and DFY is to consider the process variation effects in early stage of IC designs. If we can evaluate the impacts of circuit performance under process variations in advance, the circuit yield could be improved at early stages to reduce the re-design cycles and re-spin cost.
Design centering is one of the popular techniques for yield enhancement. Using the nominal design as an initial point, this technique gradually moves the nominal point toward better yield by using the results of circuit performance analysis so that most of simulation samples under process variations will locate in acceptable design regions. However, traditional design centering approaches often require complicated formulas and numerous design constrains to find out the boundaries of acceptable design regions. For complicated analog circuits, such approaches may be difficult to figure out the borders of feasible regions for yield enhancement.
In this thesis, a boundary-less design centering approach is proposed for phase- locked-loop (PLL) circuits, which are very sensitive to process variations. Instead of finding the borders of feasible regions, this work searches the moving tracks of nominal points by reusing the yield analysis results and some mechanics models. After finding the nominal point with better yield, the original design will be adjusted hierarchically to match that nominal point and generate a highly-reliable circuit. Because the proposed yield enhancement approach does not need the complex process to find the boundaries of feasible regions, complicated analog circuits like PLL can also be handled efficiently. As demonstrated in the experimental results, this work indeed improves the design yield of a PLL in a short time even though the PLL circuit is so complicated.
|
|---|
