Monolithic Integration Technologies for High Speed Front-end Photoreceivers

• Main Authors: Wei-kuo Huang, 黃維國
• Other Authors: Yue-ming Hsin
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/73767104420250588477

博士 === 國立中央大學 === 電機工程研究所 === 96 === This dissertation proposes several technologies for high speed monolithic front-end photoreceivers at 1550 nm and 850 nm wavelengths, respectively. Except for the requirement of the necessary high speed performance, the main idea of the proposed monolithic solutions are compatible or can be fully fabricated in standard commercial technologies without process modifications. Comparing to the hybrid approaches, the supplied advantage of the simpler package promises high yield and low parasitic effect, and thus reduces the cost. Monolithically integrated front-end photoreciever based on InP/InGaAs material system is very attractive because of the potential for high-speed operation in long-wavelength optical communication systems. Using same layer structure for photodiode (PD) and trans-impedance amplifier (TIA) provides the advantages of one-step epitaxy and simple fabrication. An example of the shared layer integration scheme in this design is the p-i-n PD/HBT photoreceiver in which the p-i-n PD is made with the base-collector layers of the HBT structure without any complex growth and fabrication sequence. In this dissertation, a conventional top-illuminated InP/InGaAs p-i-n PD/HBT structure and the integration of a PD with a single stage common base TIA are designed, fabricated and characterized. A -3 dB electrical bandwidth of 15.5 GHz is obtained for the integrated circuit though a higher bandwidth of 34 GHz is observed for the TIA only. The bandwidth of this optoelectronic integrated circuit (OEIC) is mainly limited by the characteristic of the p-i-n PD. In order to improve the response time of the PD and the inherent trade-off problem in the conventional type, the novel structure of the combined InP evanescently coupled photodiode (ECPD)/HBT is proposed and applied in the monolithically and flip-chip assembled OEICs. The ECPD/HBT approach overcomes the limitations of the PD and the trade-off problem in the conventional solution. The fabricated ECPD with a thinner absorption layer exhibits a higher responsivity of 0.3 A/W and a -3 dB electrical bandwidth of 29 GHz. The integrated ECPD/HBT receiver demonstrates a -3 dB electrical bandwidth of 38 GHz with a transimpedance gain of 32 dB-ohm. In the flip-chip assembled OEIC, it comprises an InP chip and the carrier substrate. The InP chip consists of an ECPD, an InP/InGaAs HBT and the bonding pads. The semi-insulating GaAs carrier consists of all other passive components. The OEIC demonstrates a -3 dB electrical bandwidth of 35.5 GHz with a transimpedance gain of 32 dB-ohm. Except for the long wavelength (1550 nm) application, the short wavelength (850 nm) application is also discussed to enable cost-effective implementation of optical short-distance interconnect in standard Si CMOS technology. Since Si CMOS technology provides an universal platform for monolithic integration of complex circuits and can be monolithically integrated with Si PD (850 nm) to form an all-Si optical receiver. However, the diffusion photocarriers which are generated from deep substrate diffuse slowly to the depletion region in the Si PD and result in a slow photo-response. This imposes severe limitations on the receiver architecture and performance. Hence the Si PD which is a crucial issue in CMOS OEIC is investigated and proposed. A new high-speed and high-responsivity avalanche photodiode (APD) with multiple p+-p-n diodes structure by standard TSMC 0.18 um CMOS technology is presented without any process modifications. The designed PD demonstrates a high responsivity of 0.3 A/W, a -3 dB bandwidth of 1.6 GHz, and an eye diagram at 3.5 Gb/s. Another novel method is also proposed to eliminate the slow photocarriers by using body contact design to create a current path under the PD. The novel PD with body contact (VB) of 5 V and 10 V shows higher modulation ratio than PD with floating VB. The measured eye diagram at data rate of 2.5, 4, and 5 Gb/s are also demonstrated. Finally, the monolithically integrated OEIC in standard 0.18 um CMOS technology which is based on the experience of the previous designed PDs is designed to verify the feasibility of the high speed all-Si photoreceiver. The OEIC demonstrates the -3 dB bandwidth of 4.2 GHz with VBP of 8 V. With the cable connected amplifier, the receiver shows clear eye diagram at 2.5 Gb/s and meets the mask of SONET OC-48. In the future work, the improvement of the cleaved tolerance in ECPD structure, the power dissipation in the proposed CMOS PD with body contact, the crosstalk of multi-channels application in CMOS technology, the Ge material in CMOS back-end process are proposed to further improve the current PDs and OECIs.