1-V 10-bit 2GSample/s D/A Converter based on Precision Current Reference in 90-nm CMOS

• Main Authors: HSIN-HAO WANG, 王信濠
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/96699325504527346044

碩士 === 國立中央大學 === 電機工程研究所 === 96 === Nowadays the communication applications call for high speed operation. At the same time the SoC era continuously goes on, integrating digital-to-analog converter (DAC) with DSP becomes an important tendency. In view of this, this thesis proposes a digital-analog converter which can apply to 90um CMOS technology with low supply voltage、high speed and high solution applications. For high speed operation, the work employed a fully differential architecture. The logic operation of the digital circuits must match the DAC so as to achieve the faster conversion rate. Therefore current mode logic (CML) is often used in the high speed logic design. Besides, CML can effectively reduce the even harmonics distortion and power-ground bounce. In analog circuit part, output impedance is restricted by the low supply voltage and MOS short-channel effect. Designing an accurate current mirror for current source matrix, therefore, becomes extremely difficult. For 1 volt supply voltage considering the demands, a DAC with a new high precision active cascode mirror circuit is proposed in this work. The precision of this current source array can be obtained. In addition, the demand of low supply voltage and the influence of MOS short-channel effect can be overcome. The proposed 2GS/s 10bit DAC is implemented in 90nm CMOS 1P9M technology with the supply voltage of 1 volt. The INL is ±0.32LSB, and the DNL is ±0.13LSB. When the DAC operates at an input signal frequency of 9.3MHz, a SFDR of 65.1dB can be achieved. Moreover, a SFDR of 54.4dB can be gained when the DAC operates at 982.2MHz. The power consumption of the proposed design is 79mW. The core area is 0.6mm × 0.416mm