A Low Complexity and Low Power MP3 Design with it''s SBR Extension

• Main Authors: Chia-Ying Wu, 吳佳頴
• Other Authors: Tsung-Han Tsai
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/02750079265789103920

碩士 === 國立中央大學 === 電機工程研究所 === 96 === MPEG Layer 3 (MP3) is the most popular audio compression format in the world for both hardware-based devices and software-based applications. Presently, MP3 has turned into a synonym for personalized music entertainment for millions of people. Based on the consideration of fast time-to-market, a general-purpose DSP or RISC processor is the common implementation approach for MP3 decoder. Since the hardware is not dedicated for MP3 application, some architecture parts in the processor are not utilized completely. The cost of each product is relatively high and the power dissipation is also a problem. Since the MP3 decoder is targeted to fit into a small portable, it is necessary to minimize the power consumption and cost. Identically, it is always reasonable to reduce the memory requirements since memory is expensive and consumes power. By use of the pure-ASIC approach, we can provide a consumer-economical solution for MP3 audio decoder with the advantages of low-cost and low-power design. Instead of the benefits obtained from dedicated hardware design, it still exist some improvements by well analysis on the individual features of MP3 decoding. This thesis is targeted on the architecture implementation with some proposed techniques to achieve a low power and memory-optimized design. Beside, we also design the SBR architecture using hardware sharing methods. So our design can achieve small area and high hardware utilization.