| Summary: | 碩士 === 國立中央大學 === 工業管理研究所 === 96 === In semiconductor manufacturing, getting high performance in low cost such as reducing work in process, delivery distance or delivery time, cycle time and increase yield is the most important purpose. How to get the high performance is the question. The facility layout design and AMHS, doing the best in finite space, are the questions to achieve a successful 300mm fab.
The purpose on this paper is that the products to process of the Bay must pass through the Stocker, it is almost cost a lot of time. If we can set up a Direct Transport Track within Bays to make the products pass through without Stocker. We trust that set up a Direct Transport Track can reduce transportation distance and save a lot of time. For this reason to plan the best Direct Transport Track, we must consider the IntraBay and InterBay layout.
The paper focuses on spine configuration in fab layout, and in different of other papers, it considers the IntraBay and InterBay defined. To achieve a short transportation distance both in IntraBay and InterBay, we using heuristic algorithm and mathematical model. First, we defined the machine layout of Bay by FLA method, Simulated Annealing, and Extra cost. Second, we defined the Bay layout by Visual C++ and mathematical model using CPLEX 7.0. Final, we find the Direct Transport Track also by mathematical model. Based on this analysis, we expect that the facility layout will reduce transportation distance of wafer lots, and increase equipment utility.
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