| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === With the increasing demanding of portable devices, how to use the battery energy efficiently is the most concerned problem. Therefore, power management system is indispensable for modern consumer products. For power management system, low-dropout (LDO) liner regulator is the most common block due to the characteristics, such as simplicity, small board space, low noise and cost.
Conventional LDO regulator is compensated by the equivalent series resistor (ESR). However, this kind compensation is hardly to maintain because gain and poles locations are varied with load conditions. In recent years, the demanding for high performance liner regulator such as high load regulation and high power supply rejection is getting growing. The Multi-stage LDO can achieve this target. Meanwhile, with the development of SoC system, a capacitor-free LDO is preferred to reduce the board space and cost greatly. However, the most important disadvantage of multi-stage LDO is the minimum load restriction.
Therefore, a current feedback compensation (CFC) technique for capacitor-free LDO regulators with adaptively adjusting the phase margin is proposed in this thesis. CFC technique can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50μA without sacrificing bandwidth at light load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique. The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35μm 2P4M CMOS process with small compensation capacitors 5pF and 1.5pF. Experimental results demonstrate that the minimum load can be reduced to 50μA and transient response time with adaptively phase margin control is smaller than 4μs.
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