| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === The electronic devices, such as TFT-LCD panel and digital camera, are great prevalent for customer market in the recent year. In order to provide the regulated supply voltage and extend the battery life, the power management system is utilized.
The soft-start technique is an important feature for power management system especially for the power-on sequence of dc-dc converters. It not only diminishes the inrush current to protect the converter from occurring damage but also ensure the converter to start up successfully. The conventional soft-start technique uses a large off-chip capacitor to generate gently reference voltage. However, the large off-chip capacitor occupies an external I/O pin to increase the cost and footprint area of the power module.
In this thesis, the proposed soft-start technique with nonlinear loop control provides the current-limit levels increased from zero up to the maximal current-limit value in design current steps. As a result, the specific output voltages can be raised up by characteristic current steps. The proposed technique not only has excellent constant peak current limiting capacity for any load conditions to diminish initial inrush current efficiently, but also reduces the numbers of the external I/O pins to decrease the cost of the converter without needing any external capacitors.
The proposed soft-start technique is based on the current-mode controlled boost converter with better performances than those of voltage-mode controlled converter. The converter implementation is simulated and fabricated by UMC 0.35-�慆 CMOS technology and the efficiency is 90% in the heavy load condition.
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