A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication

碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === This thesis proposes an optimal method to reduce the power consumption and area of global interconnects by buffer insertion. In order to balance the bandwidth, the power, and the area, the figure of merit is introduced to guide the design of the global intercon...

Full description

Bibliographic Details
Main Authors:	Ying Hao Ma, 馬英豪
Other Authors:	Chau Chin Su
Format:	Others
Language:	zh-TW
Published:	2007
Online Access:	http://ndltd.ncl.edu.tw/handle/27788145600469240230

id	ndltd-TW-096NCTU5591031
record_format	oai_dc
spelling	ndltd-TW-096NCTU55910312016-05-18T04:13:14Z http://ndltd.ncl.edu.tw/handle/27788145600469240230 A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication 一個低硬體成本消耗,適用於晶片內單通道每秒三十億筆資料傳輸之匯流排介面電路設計 Ying Hao Ma 馬英豪碩士國立交通大學電機與控制工程系所 96 This thesis proposes an optimal method to reduce the power consumption and area of global interconnects by buffer insertion. In order to balance the bandwidth, the power, and the area, the figure of merit is introduced to guide the design of the global interconnects to achieve high performance. The optimal design is obtained and result is compared with HSPICE simulation. The simulation results show that at 1.8V the figure of merit increases 75% as compared to other conventional design. To verify the design, a 3Gbps for 10mm long on-chip interconnects has been designed. It is implemented in TSMC 0.18 m 1P6M CMOS process, the global interconnects consume 9.2mW on a 1.8V power supply. Chau Chin Su 蘇朝琴 2007 學位論文 ; thesis 51 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === This thesis proposes an optimal method to reduce the power consumption and area of global interconnects by buffer insertion. In order to balance the bandwidth, the power, and the area, the figure of merit is introduced to guide the design of the global interconnects to achieve high performance. The optimal design is obtained and result is compared with HSPICE simulation. The simulation results show that at 1.8V the figure of merit increases 75% as compared to other conventional design. To verify the design, a 3Gbps for 10mm long on-chip interconnects has been designed. It is implemented in TSMC 0.18 m 1P6M CMOS process, the global interconnects consume 9.2mW on a 1.8V power supply.
author2	Chau Chin Su
author_facet	Chau Chin Su Ying Hao Ma 馬英豪
author	Ying Hao Ma 馬英豪
spellingShingle	Ying Hao Ma 馬英豪 A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication
author_sort	Ying Hao Ma
title	A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication
title_short	A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication
title_full	A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication
title_fullStr	A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication
title_full_unstemmed	A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication
title_sort	low hardware overhead bus circuit design for 3gbps/ch on-chip data communication
publishDate	2007
url	http://ndltd.ncl.edu.tw/handle/27788145600469240230
work_keys_str_mv	AT yinghaoma alowhardwareoverheadbuscircuitdesignfor3gbpschonchipdatacommunication AT mǎyīngháo alowhardwareoverheadbuscircuitdesignfor3gbpschonchipdatacommunication AT yinghaoma yīgèdīyìngtǐchéngběnxiāohàoshìyòngyújīngpiànnèidāntōngdàoměimiǎosānshíyìbǐzīliàochuánshūzhīhuìliúpáijièmiàndiànlùshèjì AT mǎyīngháo yīgèdīyìngtǐchéngběnxiāohàoshìyòngyújīngpiànnèidāntōngdàoměimiǎosānshíyìbǐzīliàochuánshūzhīhuìliúpáijièmiàndiànlùshèjì AT yinghaoma lowhardwareoverheadbuscircuitdesignfor3gbpschonchipdatacommunication AT mǎyīngháo lowhardwareoverheadbuscircuitdesignfor3gbpschonchipdatacommunication
_version_	1718270880699645952

A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication

Similar Items