A low hardware overhead bus circuit design for 3Gbps/ch on-chip data communication
碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === This thesis proposes an optimal method to reduce the power consumption and area of global interconnects by buffer insertion. In order to balance the bandwidth, the power, and the area, the figure of merit is introduced to guide the design of the global intercon...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/27788145600469240230 |
| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === This thesis proposes an optimal method to reduce the power consumption and area of global interconnects by buffer insertion. In order to balance the bandwidth, the power, and the area, the figure of merit is introduced to guide the design of the global interconnects to achieve high performance. The optimal design is obtained and result is compared with HSPICE simulation. The simulation results show that at 1.8V the figure of merit increases 75% as compared to other conventional design.
To verify the design, a 3Gbps for 10mm long on-chip interconnects has been designed. It is implemented in TSMC 0.18 m 1P6M CMOS process, the global interconnects consume 9.2mW on a 1.8V power supply.
|
|---|