Design of Power Aware Data Bus Codec
碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === In this thesis, we propose a power-aware codec scheme to reduce transition activity for data bus design. The low power data bus codec consisting of transparent, inverter, XOR, and XNOR module can lead to 23 % & 6 % power reduction compared with the un-codin...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/36154066775317326758 |