| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 96 === Because of the rapid growth of wireless communication, there has been more focus on analog-to-discrete converter (ADC) for wireless communication. Since the frequency is usually narrow-band in general wireless communication, in order to reduce the complexity of the architecture, we usually require the ADC has the ability of in-band anti-noise. Besides, it is important the ADC operates in low voltage, low-power, and small area. The delta-sigma (ΔΣ) ADC is very suitable for the application because they can achieve high accuracy for narrow band signals with few analog components and insensitivity to process and component variation.
Typically, there are two kinds of ΔΣ ADCs. The first one is the discrete-time (DT) ΔΣ ADC and the other is the continuous-time (CT) ΔΣ ADC. The DT ΔΣ ADC also called the switched-capacitor (SC) ΔΣ ADC because of using switched capacitors. The CT ΔΣ ADC obtains lots of attentions lately. Because the requirement of integrator is relaxed, it does not need to process signals within a clock time. This results in further power reduction.
In order to combine the advantages of the CT ΔΣ ADC system into low-power communication system, this research focuses on low power 20MS/s sample frequency 3-rd order zero optimization CT GM-C ΔΣ ADC for GSM communication system.
The chip has been fabricated by TSMC 0.18-um CMOS process. The measured peak SNDR is 45dB, SNR is 47.8dB and the DR is 49dB. The resolution is 7.2 bits that is 4 bits lower than prediction in 200k HZ signal band.
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