An improved Interface Traps Profiling on the Study of Reliability in Strained CMOS Devices

• Main Authors: E Ray Hsieh, 謝易叡
• Other Authors: Steve S. Chung
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/08979804903200495387

碩士 === 國立交通大學 === 電子工程系所 === 96 === For the first time, an improved DC-IV measurement has been developed for the reliability study of devices with EOT down to 13A0, and also a new interface-trap lateral-profiling technique has been built. It can be used to accurately profile the interface traps distributions along the device channel. By performing the above characterization and measurements, the reliabilities of the strain CMOS have been studied, from which two conclusions have been provided: (1) For strained nMOSFETs, nitride-capped devices are appreciated in terms of reliability and performance. SSOI devices have good hot-carrier immunity and performance, but its channel interface quality has to be improved. The performance of SiC devices is good, but the junction quality is worse. The SiGe on substrate devices exhibit very good performance, but the Ge-out diffusion effect is so serious that these devices are unreliable. (2) For strained pMOSFETs, SiGe on S/D devices will be appreciated in terms of performance and reliability. Also, SiGe on channel devices have worse NBTI property. As a consequence, from the future perspective, it is necessary to make a trade-off and to find the best strategy to improve the performance and, meanwhile, keep reliability. All the results in this thesis will be valuable to provide a design guideline for designing advanced CMOS devices with both good performance and reliability.