| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 96 === As CMOS device scaling to nanometer regime, the conventional device would meet many challenges to scaling. The Schottky barrier (SB) FET becomes one of the promising structures and has better scalability. However, the on-current of SB FETs is limited by the Schottky barrier at source side. The Modified-Schottky-Barrier (MSB) FETs have been proposed to improve the SB FETs performance. Therefore, the effects of the parameters of the MSB region on device performance and series resistance optimization were simulated by TCAD tools.
According to the simulation results, the MSB FETs can be classified into two groups. One is conventional-like devices, and the other one is SB-like devices. For the conventional-likes devices, the high doping concentration and thick thickness of the MSB region would thinner the Schottky barrier thickness at the source side and increase the tunneling current. Therefore, the total conductance is dominated by the gate field induced channel potential barrier lowering. In contrast, for the SB-like devices, the MSB region with lower doping concentration and thin thickness is easily depleted by gate bias. Therefore, the Schottky barrier resistance dominates the total conductance. However, as the device scaling down, the thick MSB thickness would degrade the device performance due to the reduction of effective channel length. Thus, the MSB region with thinner thickness and high doping concentration is needed. On the other hand, the drain-induced-barrier-lowering (DIBL) has to be considered for short channel device. According to the simulation results, the DIBL increases as the MSB doping concentration increases. The optimized conditions for tri-gate MSB FETs with channel length = 32 nm are the MSB thickness = 3 nm and the MSB doping concentration = 3 ×1019 cm-3.
The contact resistance is the major part in total resistance. The MSB FETs utilize the high doping concentration at the silicon and silcide interface to reduce the contact resistance. Various silicide thickness structures were used to increase the contact area and reduce the contact resistance. For the conventional-like devices, the optimized silicide thickness is about half of the silicon thickness. For the SB-like devices, the optimized value is about 10 nm due to the tunneling current is concentrated at the Si surface; therefore, the increase of silicide thickenss would not provide additional tunneling current. For tri-gate MSB FETs, the optimized value of planar contact is about 30~35 nm (nearly fully-silicided structure) due to the sidewall channel effect. The optimized value of wrapped contact is quarter of the fin width. However, the on-current and subthreshold swing shows the same silicide thickness dependence. The tradeoff between on-current and subthreshold swing has to be considered.
The external loading method was used to extract the series resistance of simulated and real devices. For the conventional-like device, this extraction method is suitable. But for the SB-like devices, this method can not be applied. The extracted series resistance from simulation devices is 160.01 Ω-μm and the specific contact resistivity is lower than 5.5 ×10-8 Ω-cm2 (meet the requirement of ITRS roadmap). The extracted series resistance from contact resistance test structures is about 1~3 kΩ-μm and the specific contact resistivity is 6 ×10-7 Ω-cm2. The contact resistivity of real devices is one order higher than that of the simulatresulted device. The reason may be that the MSB doping concentration is not high enough as expected. The real devices still exhibits a very conventional-like property due to the thicker thickness. It is estimated to be about 10nm. The MSB region of the real devices can be conjectured by the comparison of simulation results and then to improve the process condition to optimize the device performance.
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