Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme and Self-Calibrated Voltage Scaling Technique for Network-on-Chip
碩士 === 國立交通大學 === 電子工程系所 === 96 === Because of the shrinking of processing technology, the on-chip interconnect will dominate performance of hole chip in future. Network on Chip design have been considered an effective solution to integrate multiprocessor system. In this thesis, a joint bus and erro...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/84469463213338086335 |