Capacitive Interface Circuits Evaluated by Integrating and Charging Methods

• Main Authors: Yueh-hsun Tsai, 蔡岳勳
• Other Authors: Yu-Chung Huang
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/54043962127563900522

碩士 === 國立交通大學 === 電子工程系所 === 96 === Capacitive sensors are widely adapted to various measuring equipments. The objective goal of this thesis is to design and analyze two different type of capacitive interface circuit and choose a structure to implement in discrete time model prototype chip. The architecture of integrating interface circuit is based on the switch-capacitor integrator. The charging and discharging speed varies with differential capacitance which senses the analog parameter. Through the comparator, the periodically charging and discharging behavior results in variation of duty cycle which achieve the readout of capacitance difference. The architecture can achieve high resolution. The architecture of charging interface circuit is based on switch-capacitor sample-and-hold circuit. During sample phase, the differential sensing capacitor sample two different reference voltage and redistribute them in hold phase and generate a stable output voltage. The architecture can achieve high speed, low cost, low power. In this thesis we complete the design and simulation of both architectures. From the discussion, a suitable architecture is chosen to be further implemented. The charging interface circuit is implemented with layout and discrete time model prototype chip. For 100pF nominate capacitance, the measuring range is ±100pF which correspond to voltage from 1.47V to 3.26V. The error of this capacitive interface circuit is less than 5%.