| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 96 === This thesis proposes an embedded compressor/decompressor for mobile video applications. It uses lossy compression scheme to reduce the amount of data transferring between chip and external memory. This lossy compression can maintain acceptable video quality while reduces the required size of external memory, the bandwidth requirement and the power consumption on memory access.
Proposed algorithm is composed by discrete cosine transform (DCT) with coarse grain bit-plane zonal coding (CGBPZ). The compression ratio is two. It compresses a 4x4 pixel-array into a 64 bits segment. First, the two dimensions discrete cosine transform converts 16 pixels into 16 elementary frequency components. Coarse grain bit-plane zonal coding packets the coefficients and then sends to external memory. A compensation scheme is also proposed for decoding.
Hardware architecture of the proposed algorithm is able to be embedded into video decoder and support HD1080@100MHz, 30 frames per second. Since the compression ratio is fixed at two, the coded segments have fixed size and can be randomly accessed by motion compensation unit. The gate counts are 30K synthesized by UMC 90 nm CMOS technology. It costs 72 cycles to encode a MB and 34 cycles to decode a MB. Overall reduction ratio on memory access is 40%. Comparing with the power consumed of proposed design, the amount of power saving is large.
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