| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 96 === As the very large scale integration (VLSI) technology continues to be scaled down, the thickness of gate dielectric has to be decreased for maintaining the capacitance value and drive levels. The gate leakage current increases with decreasing thickness, and the phenomenon is counter to the mobile device in the technology node. In order to obtain small threshold voltages, we would replace poly-Si gate by metal gate.
In this thesis, we improve the electrical characters of FUSI Gate-High gate dielectric-semiconductor MOSFET. We obtain good performance of proper effective work function of 4.95eV (4.25eV) for p- and n- MOSFET respectively, and about 1.6nm EOT. On the other hand, small threshold voltage and good mobility have also been measured. The thermal stability is up to 1000℃ due to the inserted Si. Unfortunately, the Fermi-Level pinning effect still occurs. However, the whole process can be used in the factory.
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