Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes
碩士 === 國立交通大學 === 電子工程系所 === 96 === This thesis proposes a scan-cell reordering scheme based on unspecified test vectors to reduce the signal transitions during test mode while preserving the don’t-care bits in the test patterns for a later optimization. First, we introduce a method that uses respon...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/9dh9zw |
| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 96 === This thesis proposes a scan-cell reordering scheme based on
unspecified test vectors to reduce the signal transitions during test mode while preserving the don’t-care bits in the test patterns for a later optimization. First, we introduce a method that uses response correlations to guide the scan cell reordering and specify don’t care bits through a pattern-filling technique to reduce scan-in transitions. Next, a proposed scheme utilizes both response correlation and pattern correlation to simultaneously minimize scan-out and scan-in transitions. A extension of
the scheme that reverse-combined technique applied to the method further reduces test power. Except power-driven scan cell reordering methodology, we last propose a methodology that takes the routing overhead into consideration and derive a new ordering methodology based on power and routing concerns. We can make a tradeoff between power and routing to reduce timing violations. A series of experiments demonstrate the effectiveness and superiority of the proposed scheme on reducing total scan-shift transitions. The effectiveness of the scheme considering both power and routing overhead is discussed through
experiments as well.
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