Coupling Capacitance and ECP-Aware Dummy Metal Fill for Layout Uniformity in Cu Process
碩士 === 國立交通大學 === 電子工程系所 === 96 === With feature sizes on chips shrinking at new process node, the difficulty in manufacturability and reliability of chips is increasing. It has necessitated better planarization of chip surface topography to improve both functional and parametric yield. The common s...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/h3927j |