| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 96 === This thesis presents the research result of an ultra low-power and high-performance 32-bit embedded processor with JPEG decoder system. This processor is named ACARM7 (ACademic ARM7). The ISA (Instruction Set Architecture) of ACARM7 adopts the ARM V4 architecture. Hence the ADS (ARM Develop Suite) can be directly used. ADS can first be used to compile the high level programming language (C, C++) written by users to the assembly language, and then can assemble the assemble language to the low level machine code for ACARM7 use. It indicates the high usability of ACARM7. Compared with ARM7TDMI, the power consumed by the proposed processor is lower; the gate-count of the proposed one is less; and the performance is better. Meanwhile, this thesis also provides a thorough and rigorous verification flow which assures both the correctness of functional behavior of the proposed processor design after more than two billion simulation cycle comparisons and the synthesis correctness of synthesized gate-level netlist circuit. Moreover, the proposed processor is mapped onto the FPGA and integrated within the ARM926EJ-S Versatile Development Board to implement a JPEG decoder system. Based on the experiment result obtained by this research, the higher performance, the smaller area, and the lower power are all the advantages of the proposed processor compared with ARM7TDMI. The thesis also proposes a thorough and rigorous processor verification flow. Moreover, the high applicability of the proposed processor is demonstrated by mapping it into an FPGA for implementing a JPEG decoder system.
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