The Study of Software-defined Phase-locked Loop

• Main Authors: Cheng-Ying, Chuang, 莊承穎
• Other Authors: Terng-Yin Hsu
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/14873205745400131352

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 96 === This paper is proposed to the platform of software defined phase locked loop. The platform is combined of OPENRISC and the all-digital phase locked loop. There are three major issues in this platform: the interface, the intellectual property (IP) based design and the software algorithm. First, the interface is used for synchronization, communication and controlling. Second, the time-to-digit converter is one of IP in the all-digital phase locked loop. We propose the time-to-digit converter which resolution is 1ps without the parasitical capacitance and parasitical resistance. Finally, the topic of software algorithm is the cycle count. The platform needs 5 cycles to lock the frequency and the phase. This platform has good performance at the reusability, the process portability, and flexibility. The platform can reduce the design cost, especially at time. We implement this platform on Faraday 90nm process.