| Summary: | 碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 96 === In this thesis, a high-speed and low-complexity design of multi-mode Reed-Solomon codec is proposed. In the beginning of deliberating algorithms, the policy is to simplify the coefficients of equations, so as to construct a simpler structure.
The proposed RS decoder has some major features introduced as following：
1. In the SC block, a simpler t-decoder is exploited to dominate the sixteen cells, so as to answer to multi-mode applications.
2. In the KES, the “Decision Variations” is proposed to break the main speed bottleneck of iBMA in the iterative computation of discrepancies followed by updating the correction polynomial and to prevent the special-case data hazard in the most serial structures. Also, for the sake of keeping the critical path in the reusing hardware is still Tmult+Txor, the assimilative coefficient knack is adopted. Further, we use the purpose-built address line to simplify the hardware complexity of storage element
3. In Chien’s Search and Forney’s block, fifteen Compensators used to adjust the starting point of search are reduced to one and combined in the KES block.
After 204.8 hundred-million bits transmission and verification regular, the proposed RS decoder for multi-mode applications (n<=255, t<=8) is implemented by Xinlinx VirtexE xcv2000e FPGA and Synopsys DC with UMC018 library. The design possesses higher speed and lower gate count than present decoder design. The data rate of the proposed decoder is 5.84bps at the maximum clock rate of 730MHz with 11596 gates.
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