An Approximate Square Prediction Criterion for H.264/AVC Mode Decision and Its VLSI Implementation

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === In this thesis, we propose an approximate square prediction criterion for H.264/AVC mode decision. Sum of absolute difference (SAD) and sum of squared difference (SSD) are two popular prediction criteria in the spatial domain. SSD achieves better video quality...

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Main Authors: Kuan-Hung Lin, 林冠宏
Other Authors: Bin-Da Liu
Format: Others
Language:en_US
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/43285585003706455668
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spelling ndltd-TW-096NCKU54421532017-08-02T04:22:22Z http://ndltd.ncl.edu.tw/handle/43285585003706455668 An Approximate Square Prediction Criterion for H.264/AVC Mode Decision and Its VLSI Implementation 用於H.264/AVC模式決策之近似平方預測法則及其VLSI實現 Kuan-Hung Lin 林冠宏 碩士 國立成功大學 電機工程學系碩博士班 96 In this thesis, we propose an approximate square prediction criterion for H.264/AVC mode decision. Sum of absolute difference (SAD) and sum of squared difference (SSD) are two popular prediction criteria in the spatial domain. SSD achieves better video quality than SAD due to the square computation. The square operations take high computational complexity and large hardware cost. An efficient mode decision criterion is proposed to maintain the video quality compared to SSD. The proposed criterion much reduces the computational complexity and improves hardware performance by using a first-one-detector and shifter. Simulation results show the total number of logic gates is 31.2k, and the core size of layout is 435,786 μm2. The proposed intra prediction architecture takes 1,078 clock cycles to predict one macroblock. The proposed architecture using the SASD criterion reduces more than 30% critical time delay compared with that using SSD. The maximum operation frequency is 133 MHz. For the real-time requirement, the maximum frame size achieves 720p HD (1280×720)@30 frames/sec while the sequence format is 4:2:0. Bin-Da Liu Jar-Ferr Yang 劉濱達 楊家輝 2008 學位論文 ; thesis 77 en_US
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description 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === In this thesis, we propose an approximate square prediction criterion for H.264/AVC mode decision. Sum of absolute difference (SAD) and sum of squared difference (SSD) are two popular prediction criteria in the spatial domain. SSD achieves better video quality than SAD due to the square computation. The square operations take high computational complexity and large hardware cost. An efficient mode decision criterion is proposed to maintain the video quality compared to SSD. The proposed criterion much reduces the computational complexity and improves hardware performance by using a first-one-detector and shifter. Simulation results show the total number of logic gates is 31.2k, and the core size of layout is 435,786 μm2. The proposed intra prediction architecture takes 1,078 clock cycles to predict one macroblock. The proposed architecture using the SASD criterion reduces more than 30% critical time delay compared with that using SSD. The maximum operation frequency is 133 MHz. For the real-time requirement, the maximum frame size achieves 720p HD (1280×720)@30 frames/sec while the sequence format is 4:2:0.
author2 Bin-Da Liu
author_facet Bin-Da Liu
Kuan-Hung Lin
林冠宏
author Kuan-Hung Lin
林冠宏
spellingShingle Kuan-Hung Lin
林冠宏
An Approximate Square Prediction Criterion for H.264/AVC Mode Decision and Its VLSI Implementation
author_sort Kuan-Hung Lin
title An Approximate Square Prediction Criterion for H.264/AVC Mode Decision and Its VLSI Implementation
title_short An Approximate Square Prediction Criterion for H.264/AVC Mode Decision and Its VLSI Implementation
title_full An Approximate Square Prediction Criterion for H.264/AVC Mode Decision and Its VLSI Implementation
title_fullStr An Approximate Square Prediction Criterion for H.264/AVC Mode Decision and Its VLSI Implementation
title_full_unstemmed An Approximate Square Prediction Criterion for H.264/AVC Mode Decision and Its VLSI Implementation
title_sort approximate square prediction criterion for h.264/avc mode decision and its vlsi implementation
publishDate 2008
url http://ndltd.ncl.edu.tw/handle/43285585003706455668
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