A 3-V 28-mW 10-bit 20-MSample/s Pipeline ADC Without Using a Front-End Sample-and-Hold Amplifier
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === This thesis describes a low power 10-bit 20-MS/s pipeline analog-to-digital converter (ADC) implemented in TSMC double-poly four-metal 0.35-μm CMOS technology. A new configuration at the first pipeline stage avoids using a dedicated sample-and-hold amplifier (...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37399629750489336062 |
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