A 3-V 28-mW 10-bit 20-MSample/s Pipeline ADC Without Using a Front-End Sample-and-Hold Amplifier
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === This thesis describes a low power 10-bit 20-MS/s pipeline analog-to-digital converter (ADC) implemented in TSMC double-poly four-metal 0.35-μm CMOS technology. A new configuration at the first pipeline stage avoids using a dedicated sample-and-hold amplifier (...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/37399629750489336062 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === This thesis describes a low power 10-bit 20-MS/s pipeline analog-to-digital converter (ADC) implemented in TSMC double-poly four-metal 0.35-μm CMOS technology. A new configuration at the first pipeline stage avoids using a dedicated sample-and-hold amplifier (SHA). The ADC employs a wide-swing, gain-boosted folded-cascode amplifier to further reduce power consumption. In addition to compensating for capacitor mismatch with a commutated feedback capacitor switching (CFCS) technique, the ADC introduces gate-bootstrapping switches to sample inputs with frequencies comparable to its sampling rate. The simulated differential and integral nonlinearity of the ADC are within 0.31 least significant bit (LSB) and 0.45-LSB respectively at full sampling rate. It exhibits higher than 9.5 effective number of bits (ENOB) for an input frequency at Nyquist (fin = 10-MHz). The ADC core consumes 28-mW including the on-chip voltage reference from a 3-V supply and occupies an area of 0.76-mm2.
|
|---|