Design and Implementation of Efficient Pattern Matching Architectures in FPGA

• Main Authors: Yu-ru Chung, 鍾宇儒
• Other Authors: Yeim-Kuan Chang
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/33338530085688262235

碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 96 === With the growth of internet, more and more attacks and viruses spread in the net, we usually use NIDS system to detect those attacks or viruses and help us to protect our system. Pattern match algorithm play an important role for NIDS system, we need to use pattern match algorithm to found those attacks and virus hidden in the payload of packets efficiently, in order to suit the internet speed, software-based algorithm may not process so many packets in short time, hardware-based architecture is needed, in our thesis, we proposed an efficiency pattern match architecture which can use less area cost then multi-character processor array architecture, and also have 5Gbps throughput, the main idea is when prefix of pattern matched, we load suffix characters to continue following comparisons, we use the same hardware to process suffix. But suffix in multi-character processor array may need several PE according to suffix length, as pattern length increase, our architecture can use hardware resource than multi-character processor array, and keep acceptable processing speed.