| Summary: | 碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 96 === The representation of most multimedia systems involves a vast amount of data, so it is inevitable to reduce the data rate for compression. Variable length coding (VLC) is a very popular lossless compression method and it has been used into many image and video coding standards. In the thesis, we present an area-efficient variable length decoder (VLD) for MPEG-1/2/4. Generally, the VLD design needs a large coding table to perform the decoding procedure, and it is implemented with larger storage space. Hence, its hardware cost quite high and unacceptable.
For reducing the hardware cost, we propose an efficient implementation method in this thesis. First, the highly correlated symbols are grouped into the same cluster. Then, we use the table merging approach to reduce the storage space of LUTs needed for MPEG-1/2/4. In the design, the size of a single LUT and the total number of LUTs required for MPEG-1/2/4 are both reduced efficiently. Thus our design achieves the target of low hardware cost.
The VLSI architecture of our MPEG-1/2/4 VLD was implemented by using Verilog HDL. We used Design Vision to synthesize the design with TSMC 0.18μm cell library. The layout for the design was generated with Astro. The chip area is 1310x1310μm2, and the clock rate is 125 MHz. Our VLD is fast enough to support video resolution of HD1080 at 30 fps for MPEG-1/2/4 real-time decoding.
|
|---|
