| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 96 === This thesis designs a high speed digital-to-analog converter (DAC). The DAC architecture uses binary-weighted current steering. In order to achieve high output impedance to improve DNL and INL, we step down the control signal of the switch on the current source. Additionally, we design a reshaping circuit to improve the distortion of signal when the circuit operates in high speed. In this way, we can reduce the effect of glitch. The architecture of the binary weighted DAC consists of a latch, a current cell, a step down circuit and a signal reshaping circuit.
It is simulated by TSMC 0.18 um standard CMOS technology, the supply voltage is 1.8 V. DNL is about ±0.09 LSB, INL is about ±0.6 LSB. At 2 GS/s, the spurious-free dynamic rang (SFDR) of 38.9 dB can be achieved with 875 MHz, and the spurious-free dynamic rang (SFDR) of 37.3 dB can be achieved with 87.9 MHz. The power dissipation is 5.44 mW.
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