Automatic baseline driver generator for fast IP integration in SoC designs

Automatic baseline driver generator for fast IP integration in SoC designs

碩士 === 國立中興大學 === 電機工程學系所 === 96 === This paper presents the framework of a baseline driver generator to facilitate the driver development for fast IP integration in SoC designs. The proposed baseline driver generator can handle both character and block type devices and is found useful for the integ...

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Bibliographic Details
Main Authors:	Chun-Chieh Chiu, 邱俊傑
Other Authors:	黃穎聰
Format:	Others
Language:	zh-TW
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/03035358225249828426

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