Reducing Static and Dynamic Power in Scan Testing

• Main Authors: Shun-Jie Huang, 黃順傑
• Other Authors: Sying-Jyan Wang
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/67029547627699981970

碩士 === 國立中興大學 === 資訊科學與工程學系 === 96 === Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique for static and dynamic power reduction in the scan test process. The leakage current is restrained by selecting a good primary input vector to control the paths of leakage current in the scan shift process. The proposed method is simulated by SPICE with BPTM 22nm technology, and the results show that on the average 15% total power reduction is achievable by the proposed method. By our analysis, because of large amount of the inverters, and no matter in which input signal the leakage current of an inverter is quite large, so the reduced amount of average power is restrained.