Analysis of Device Integrity with Micro-Cleaving Technology in Advanced Copper Process

• Main Authors: KenLo, 羅智勤
• Other Authors: 王木俊
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/83874521010753102321

碩士 === 明新科技大學 === 電子工程研究所 === 96 === Through the quick development in process technology, the semiconductor devices are gradually smaller. Furthermore, the width of metal lines is more and more narrow and the number of metal layers is increased more. Every fabrication company is trying to search more effective and precise method, to obtain technology and process improvement. In early period, the polisher machine plus focus-ion-beam (FIB) equipment was the only one choice to view the failure location. However, while the semiconductor process adopts the copper process in nano-scale technique, it faces many tremendous barriers. For instance, one of them is how to monitor the alloy quality of copper interconnection after annealing. The copper material basically exhibits the great extension ability so that the cross-section of copper interconnection can not be obviously observed. Next, in semiconductor fabrication, the abnormal implant is occasionally happened and induces the soft failure in device operation. This failure mechanism is able to be scanned by the scanning capacitance microscope (SCM). However, the sample in SCM system is not easily processed because the native oxide will grow and degrade the sample quality. Using micro-cleaving SELA-MC-600i setup, the sample quality is not only improved, but the sample processing time is shortened. The quality of copper deposition with electro-plating technology and the alloy performance after annealing is able to be inspected and tested. The doping profile of a MOS device may be explored, too.