Shift of Maximum Substrate Current in 90nm NMOS Device
碩士 === 明新科技大學 === 電子工程研究所 === 96 === Abstract Along with manufacturing process technique continuously innovative, including the thickness of gate oxidation layer, chip size, channel length, etc., all unceasingly downsize fast. However, the decrease of the operation voltage of the device is unable...
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| Format: | Others |
| Language: | zh-TW |
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2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95585919140493964578 |