| Summary: | 碩士 === 明新科技大學 === 電子工程研究所 === 96 === In this thesis, we use TSMC 0.35μm SiGe BiCMOS technology to design and implement a practical limiting amplifier gain post-amplifier circuit. Limiting amplifier is the back-end component of the optical communication receiver, the main design key for obtains the high gain and the high dynamic-range as well as the good stability. Also with high sensitivity to enlarge the small signal which from front-end transimpedance amplifier to the stabilized amplitude output.
We design the limiting amplifier consists with three stages, they were limiting amplifier, JAM buffer, and PECL output buffer, respectively. In this work, the total consumed power is 289mW as the supply voltage is 5V. In the mean time, the output stage can drive 50Ω loaded resistors, and the smallest input voltage sensitivity is 3.5mV. Limiting amplifier gain could also reach to 55dB and 289MHz bandwwidth, which is well suitable for application in 155M/bps optical communications. Chip size is 600μm × 600μm.
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