| Summary: | 碩士 === 崑山科技大學 === 電子工程研究所 === 96 === This article takes advantages of re-configurability, built in block RAM and embedded processor from a FPGA chip, to design a FIFO_based stream video signal procession accelerator IP. The accelerator IP can be packed into a general propose stream video co-processor which is used in SOC-based video signal procession application in form of software control.
This work presents an independent real-time platform for retrieval, processing, scaling and VGA display of stream video signal, which can be utilized in real-time surveillance system image display. This platform simultaneously provides four sets of analog camcorder video inputs and processing. The image refreshing rate is above 30 frames per second. Operated under four analog camcorders, the platform IP only occupies 30% system hardware resources.
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