SOC BUS System Design and Implementation
碩士 === 義守大學 === 電子工程學系碩士班 === 96 === This paper is aimed at single layer and multi layer soc bus system that include visual master module、dynamic reconfigurable arbiter、output control module and system control method. The visual master module simulate master’s behavior and signal in soc when transfo...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/13191941163047862606 |
| Summary: | 碩士 === 義守大學 === 電子工程學系碩士班 === 96 === This paper is aimed at single layer and multi layer soc bus system that include visual master module、dynamic reconfigurable arbiter、output control module and system control method. The visual master module simulate master’s behavior and signal in soc when transform data. Combine four popular algorithm to dynamic reconfigurable arbiter including fix-priority 、 round-robin(RR) 、 first come first service(FCFS) 、 random access(RA) algorithm. The dynamic reconfigurable is more flexibility and variable than just only one algorithm arbiter. The output control method means a output decode module. The purpose soc bus system use handshake control method. The master which is using bus will make control signal to busy and disable arbiter until master finish its work. The purpose bus system use hardware distribution language (verilog) to complete and use C language to simulate the effect that use different traffic pattern. We also use primepower to analysis power consumption in different traffic pattern. Finally use design vision support by CIC to transform bus system to gate-level netlist and use SOC encounter to transform bus system from gate-level netlist to layout.
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