Hardware/Software Co-design of AES Algorithms Using Custom Instructions
碩士 === 輔仁大學 === 電子工程學系 === 96 === The Advanced Encryption Standard (AES) is the new encryption standard appointed by NIST. To shorten the encryption/decryption time of plenty of data, it is necessary to adopt the algorithm of hardware implementation; however, it is possible to meet the requirement f...
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| Format: | Others |
| Language: | zh-TW |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/35389142457501490628 |
| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 96 === The Advanced Encryption Standard (AES) is the new encryption standard appointed by NIST. To shorten the encryption/decryption time of plenty of data, it is necessary to adopt the algorithm of hardware implementation; however, it is possible to meet the requirement for low cost by completely using software only. How to reach a balance between the cost and efficiency of software and hardware implementation is a question worth of being discussed. In this paper, we implemented the AES encryption algorithm with hardware in combination with part of software using the custom instruction mechanism provided by the Altera NiosII platform. We completed a parameterized synthesizable design. Given a parameter setting, our system can generate the hardware design and necessary software/hardware interface automatically. We explored various combinations of hardware and software to realize AES algorithm and discussed possible best solutions of different needs.
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