Bandpass Filter Design for ECG Measurement

• Main Authors: Pai-Chin Lai, 賴百勤
• Other Authors: Shyue-Kung Lu
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/43674104485476562027

碩士 === 輔仁大學 === 電子工程學系 === 96 === The ECG (Electrocardiogram) provides useful information to the condition of heart. The signal is often difficult to measure because of their weak intensity, is easily interferenced by noise. In order to get ECG signal clearly, a high quality band-pass filter is needed in measurement to remove the noise. The aim of this thesis is to design a band-pass filter with a passband about 10~30Hz, and the characteristics of filters won’t be affected by processing variation or external noise. In this thesis, we design an instrumentation amplifier (INA) as input stage to reduce common mode noise in the input signal. Then we design a biquad filter using Butterworth approximation. In order to enhance the accuracy of the frequency response characteristics in the filter, and reduce variation of the electrical characteristics by gradient effects, we replace the passive elements in the biquads by switched-capacitor circuit for the ECG measurement. The circuit in this thesis is including an instrumentation amplifier, a 4-order high-pass filter, an 8-order low-pass filter, a non-overlapping clock generator, and a current reference circuit. In the design flow, we have to decide the transfer function of filters first, and verify the transfer function by its frequency response graph with MATLAB. After the verification we transfer those coefficients of a transfer function into circuit, and simulate its transient response by H-spice, to sketch the frequency response of the band-pass filter at physical level. The center frequency of the band-pass filter is set to 20Hz with 0dB gain. The lower and higher cutoff frequencies are set to 7Hz and 35Hz, and the attenuation of the filter must be greater than 30dB when the input signal is under 1Hz or higher than 60Hz. These circuits will be fabricated in EPISIL 0.8μm CMOS 2P1M process to verity the design.