| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 96 === Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. Pre-charge Masked Reed-Muller Logic (PMRML) is one of the countermeasures which can counteract the DPA attacks. In this thesis, we use PMRML to implement a DPA-resistant AES hardware design. The key feature is that it provides multiple modes of operation, including ECB, CBC, OFB and CTR modes. We explored the design trade-off in terms of area, performance and security under different modes of operation. We implemented designs under cell-based design flow with TSMC 0.18um technology.
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