Functiional Self High-Precision Speed-Binning Mechanism for IP Cores with Multi-Voltage and Multi-Clock in SoC Chip
碩士 === 逢甲大學 === 電子工程所 === 96 === VLSI’s process and design technology advances have been developed to have high speed and System-on-a-Chip (SoC). However, the complexity of circuit design has increased, and the circuit testing has new challenges. It is very difficult to control and test internal cir...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09637823135724971833 |