Efficient Obstacle-Avoiding Octagonal Steiner Tree Construction

碩士 === 逢甲大學 === 資訊工程所 === 96 === With manufacture improvement, the same feature size could have more transistors than before. The design becomes more complex, and the timing delay problem is even more crucial. In chip design, the routing problem plays an important role of the IC performance. Effecti...

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Main Authors: Zhe-ming Ho, 何哲名
Other Authors: De-Sheng Chen
Format: Others
Language:zh-TW
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/10460795255431548192
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spelling ndltd-TW-096FCU053920572015-11-27T04:04:43Z http://ndltd.ncl.edu.tw/handle/10460795255431548192 Efficient Obstacle-Avoiding Octagonal Steiner Tree Construction 避開障礙物的有效史坦那樹建構 Zhe-ming Ho 何哲名 碩士 逢甲大學 資訊工程所 96 With manufacture improvement, the same feature size could have more transistors than before. The design becomes more complex, and the timing delay problem is even more crucial. In chip design, the routing problem plays an important role of the IC performance. Effective algorithms to reduce total wirelength become very critical and necessary for IC design. This study is to propose a new algorithm to construct X-architecture steiner tree. The algorithm not only reduces total wire length but also lowers timing delay problem. This method is different from traditional Rectilinear-steiner tree construction style that it considers not only horizontal and vertical direction, but also 45 and 135 degree routing. This study has three steps: 1. Construct Obstacle-Avoiding spanning graph. 2. Transform the spanning graph into spanning tree by Prim’s algorithm.3. Efficient obstacle-avoiding octagonal steiner tree construction method is utilized to transform the spanning tree to X-architecture Steiner tree. Though the algorithm used might result in long time than other methods, but it reduce total wire length than other papers. De-Sheng Chen 陳德生 2008 學位論文 ; thesis 45 zh-TW
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description 碩士 === 逢甲大學 === 資訊工程所 === 96 === With manufacture improvement, the same feature size could have more transistors than before. The design becomes more complex, and the timing delay problem is even more crucial. In chip design, the routing problem plays an important role of the IC performance. Effective algorithms to reduce total wirelength become very critical and necessary for IC design. This study is to propose a new algorithm to construct X-architecture steiner tree. The algorithm not only reduces total wire length but also lowers timing delay problem. This method is different from traditional Rectilinear-steiner tree construction style that it considers not only horizontal and vertical direction, but also 45 and 135 degree routing. This study has three steps: 1. Construct Obstacle-Avoiding spanning graph. 2. Transform the spanning graph into spanning tree by Prim’s algorithm.3. Efficient obstacle-avoiding octagonal steiner tree construction method is utilized to transform the spanning tree to X-architecture Steiner tree. Though the algorithm used might result in long time than other methods, but it reduce total wire length than other papers.
author2 De-Sheng Chen
author_facet De-Sheng Chen
Zhe-ming Ho
何哲名
author Zhe-ming Ho
何哲名
spellingShingle Zhe-ming Ho
何哲名
Efficient Obstacle-Avoiding Octagonal Steiner Tree Construction
author_sort Zhe-ming Ho
title Efficient Obstacle-Avoiding Octagonal Steiner Tree Construction
title_short Efficient Obstacle-Avoiding Octagonal Steiner Tree Construction
title_full Efficient Obstacle-Avoiding Octagonal Steiner Tree Construction
title_fullStr Efficient Obstacle-Avoiding Octagonal Steiner Tree Construction
title_full_unstemmed Efficient Obstacle-Avoiding Octagonal Steiner Tree Construction
title_sort efficient obstacle-avoiding octagonal steiner tree construction
publishDate 2008
url http://ndltd.ncl.edu.tw/handle/10460795255431548192
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