A study of jitter of high data transition rate and its improvement

• Main Authors: Tien-chieh Huang, 黃添傑
• Other Authors: T. K. Kang
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/50453827786985005578

碩士 === 逢甲大學 === 資訊電機工程碩士在職專班 === 96 === In order to understand the relationship between Simultaneous Switching Noise (Called “SSN”) and Data Dependent Jitter (Called “DDJ”), we use a four bits output system and simulate it by ADS tool to detail describe how SSN is one of major issue of DDJ. We propose a current balance method to reduce SSN without changing slew rate of output driver and adding silicon area for extra pads requirement. With a four bits output system, Data Dependent Jitter is reduced from 270PS to 170PS. On the other hand, Both of Partial Current Balance and Partial Control Slew Rate are used to optimize output waveform to further improve DDJ. A four bit output system has been simulated in TSMC 0.18um Model and. the simulation result show data-dependent jitter is reduced from 270PS to 30PS at 500MHz. The improving ratio is almost over 88.9%. And DDJ is reduced from 210PS to 60PS at 1GHz. The improving ratio is almost over 71.4%.