Design and Construct Full Duplex (Record/Live/Playback) Multi-Video Inputs System by ARM and DSPs
碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 96 === In recently, most of the surveillance systems have been PC-based. Unfortunately, PC-based systems are expensive to build and waste resources such as power and space. This paper focus on reducing costs without losing any features. The tradeoff to this cheaper imp...
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ndltd-TW-096CYUT53920382015-11-27T04:04:14Z http://ndltd.ncl.edu.tw/handle/68190494091169241234 Design and Construct Full Duplex (Record/Live/Playback) Multi-Video Inputs System by ARM and DSPs 使用ARM和DSPs系統設計及建置全雙工多影像輸入系統 Yang-Yu Yeh 葉永譽 碩士 朝陽科技大學 資訊工程系碩士班 96 In recently, most of the surveillance systems have been PC-based. Unfortunately, PC-based systems are expensive to build and waste resources such as power and space. This paper focus on reducing costs without losing any features. The tradeoff to this cheaper implementation is that some performance will inevitably be lost relative to the PC-based system. Most of the embedded system based DVR (Digital Video Recorder) are slow and are not full-duplex. For instance, recording, playback, and live network streaming cannot all be run simultaneously due to design constraints. These constraints are a result of insufficient memory and limitations in the CPU’s computational power. Keywords : Intel IXP 425 Processors, Altera Cyclone FPGA, Analog Devices Blackfin BF561 Processors, Linux Kernel 2.6, Techwell 2835/2836, Digital Video Recorder Honda Chen 陳宏達 2008 學位論文 ; thesis 94 zh-TW |
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碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 96 === In recently, most of the surveillance systems have been PC-based. Unfortunately, PC-based systems are expensive to build and waste resources such as power and space. This paper focus on reducing costs without losing any features. The tradeoff to this cheaper implementation is that some performance will inevitably be lost relative to the PC-based system. Most of the embedded system based DVR (Digital Video Recorder) are slow and are not full-duplex. For instance, recording, playback, and live network streaming cannot all be run simultaneously due to design constraints. These constraints are a result of insufficient memory and limitations in the CPU’s computational power.
Keywords : Intel IXP 425 Processors, Altera Cyclone FPGA, Analog Devices Blackfin BF561 Processors, Linux Kernel 2.6, Techwell 2835/2836, Digital Video Recorder
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Honda Chen |
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Honda Chen Yang-Yu Yeh 葉永譽 |
author |
Yang-Yu Yeh 葉永譽 |
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Yang-Yu Yeh 葉永譽 Design and Construct Full Duplex (Record/Live/Playback) Multi-Video Inputs System by ARM and DSPs |
author_sort |
Yang-Yu Yeh |
title |
Design and Construct Full Duplex (Record/Live/Playback) Multi-Video Inputs System by ARM and DSPs |
title_short |
Design and Construct Full Duplex (Record/Live/Playback) Multi-Video Inputs System by ARM and DSPs |
title_full |
Design and Construct Full Duplex (Record/Live/Playback) Multi-Video Inputs System by ARM and DSPs |
title_fullStr |
Design and Construct Full Duplex (Record/Live/Playback) Multi-Video Inputs System by ARM and DSPs |
title_full_unstemmed |
Design and Construct Full Duplex (Record/Live/Playback) Multi-Video Inputs System by ARM and DSPs |
title_sort |
design and construct full duplex (record/live/playback) multi-video inputs system by arm and dsps |
publishDate |
2008 |
url |
http://ndltd.ncl.edu.tw/handle/68190494091169241234 |
work_keys_str_mv |
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