ANALYSIS AND IMPROVEMENT OF INSERTED AND BUTTING SUBSTRATE PICKUP LAYOUT STYLE IN ESD NMOS DEVICES

• Main Authors: Po-Kuan Sung, 宋柏寬
• Other Authors: Chih-Yao Huang
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/73658408024279641610

碩士 === 清雲科技大學 === 電子工程研究所 === 95 === The multi-finger ESD NMOS that the butting or inserted layout of the substrate/well pickups of MOSFETs strictly degrades ESD robustness owing to the substrate resistance shorting effect. Therefore, this thesis studies on this layout restriction issue in detail. Extrinsic well/diffusion resistance insertion between the NMOS substrate body and ground can greatly improve the ESD performance degradation. Hence, we design eight types of the NMOS multi-finger layout plots, in order to obtain mechanism parameters and improve ESD performance. In the simulation part, we focus on the butting NMOS structure, and compare to the gate-grounded NMOS. The analysis results imply that butting substrate pickup leads to small substrate resistance, so that the parasitic NPN BJT can hardly turn on, and thus reduce the ESD robustness of the NMOS device.