| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 96 === As process technology scales to nano-meter, the leakage power dissipation has become an important concern for low power design in VLSI. Dual threshold voltage assignment is a popular effective technique to reduce leakage power. In this paper, we propose novel efficient algorithm to deal with this problem. We develop a level-based algorithm to decrease the time spent by high threshold voltage assignment. In addition to leakage power reduction, circuit reliability is another important issue with technology process scaling down, because the negative bias temperature instability (NBTI) of PMOS device becomes serious as gate oxide become thinner. The NBTI leads to threshold voltage degradation of PMOS over a period of months or years such that cell delay increase over a period of months or years. Therefore, the circuit will have timing violation after a long time operation. In order to deal with this problem, designer normally leave timing margin to ensure that there is no timing violation in the circuit after a long period of time. Nonetheless, different circuits still have different lifetime under the same timing margin. In order to deal with this problem, we also propose reliability oriented multiple-Vth assignment algorithm. Our algorithm has the following two important features:
(1)Due to the effective weight definition, we still can greatly save the leakage power consumption after circuit reliability improvement.
(2)Due to level-based assignment, we can decrease much time spent by high threshold voltage assignment.
Finally, the results show that our algorithm can extend circuit lifetime to 10 years for all circuit under 5% timing margin and save 52.8% leakage power in average.
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