| Summary: | 碩士 === 中華技術學院 === 電子工程研究所碩士班 === 96 === MCS51 compatible micro-processor has been launched for many years. However, it seems to be the major MCU (micro controller unit) commonly used in the low-end industrial control and simple consumer electronics products. Many semiconductor corporations have developed different MCUs, usually for their customized requirements, modified from the standard MCS51 MCU. In this paper, we use a FPGA chip to implement a MCS51 compatible micro-processor. After analysis of the project, we revised the access method of SFR (Special Function Register). Due to the multiple buses built in, we may access multiple registers at the same time. Because of the change of bus structure, we also have to modify addressing mode and operation of some instructions. After the improvement, we can increase the maximum system clock rate and decrease machine cycle time. Finally, we have finished the project with suitable synthesis and verification.
The performance of the soft core is improved due to the synchronous circuit design, doubled maximum system clock rate compared with standard MCS51, and less execution of the instructions.
In this project, we reduce circuit complexity, cost and power consumption. Companied with the other embedded peripherals as control units, the FPGA becomes a SOC chip.
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