Implementation of One-Tap RLS FDE Combined with Viterbi Decoder Using Channel State Information for DSRC Systems
碩士 === 長庚大學 === 電機工程學研究所 === 96 === In this paper, we focus on hardware implementation in FPGA for the receiver of Dedicated Short-Range Communications(DSRC) system. The hardware implementation includes novel one-tap frequency domain equalizer, De-mapping, De-interleaving, Viterbi decoder, and compa...
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| Format: | Others |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/46461324376357000118 |
| Summary: | 碩士 === 長庚大學 === 電機工程學研究所 === 96 === In this paper, we focus on hardware implementation in FPGA for the receiver of Dedicated Short-Range Communications(DSRC) system. The hardware implementation includes novel one-tap frequency domain equalizer, De-mapping, De-interleaving, Viterbi decoder, and comparing circuit. We refer to our published results of research for the algorithm of receiver. Frequency domain equalizer in DSRC systems is designed by the modified traditional RLS algorithm that can avoid division operation. And the hardware structure of equalizer is based on pipeline. Besides, the equalizer algorithm can provide the channel state information (CSI) for Viterbi decoder without additional computation. Finally, we test the hardware with some modes of DSRC. And we will compare the output data of hardware with software simulation results.
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