Design of a FIFO for Data Transfer between Multiple Clock Domains

• Main Authors: Jian Syun Huang, 黃建勳
• Other Authors: J. D. Lee
• Format: Others
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/05799594461902248625

碩士 === 長庚大學 === 電機工程學研究所 === 96 === In present System-on-Chip(SOC) design, as the wire length and the process difference ,the distribution of a synchronous clock has been a problem . One solution is to use Globally Asynchronous, Locally Synchronous (GALS) to partition the system into several synchronous blocks. Furthermore, these blocks can communicate with others by using the FIFOs. An implementation and an improvement of two novel FIFO architecture is presented here. These kind of FIFO architecture are suited to interface two systems with different clock frequency and phase. As its interfaces are synchronous, these architecture are called “bi-synchronous FIFO”and “Synchronous-Synchronous FIFO”. These two FIFOs mainly store its data by means of registers, and use the token ring circuit to create appropriate token signals which can control the FIFO write and read data in the correct clock cycle without using the Handshake circuit. Additionally, FIFO’s throughput and area are determined by its depth. Finally, the main features of these two FIFO are low latency, robustness to metastability, small area.