| Summary: | 碩士 === 長庚大學 === 電機工程學研究所 === 96 === Modern SOC (System On Chip) methodology gradually changes all synchronous circuits into GALS. Because data among different synchronous circuits transmit in asynchronous structure, how to make transmit correctly becomes a focal point. This thesis proposes a new FIFO (First In First Out) structure, three-dimension asynchronous FIFO. Pulse controlled is not needed for this type of FIFO, but an outside signal. It is very convenient to use. Need only outside offering signals of writing or reading, response of data transmission will finish by FIFO control circuit automatically. Serve as the connecter between two circuits of different pulse. Compared with traditional FIFO structure, the three-dimension asynchronous FIFO has characteristic that is low-latency and high-throughput. Adopt a special kind of asynchronous circuit, GasP structure (been used for controlling simply pipelines and domino circuits), to design its control circuit. Finally, we simulate this FIFO structure with HSPICE in TSMC 0.18μm CMOS process.
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