Three Dimensional Device Simulation of DRAM Device

• Main Authors: Yu Jen Wang, 王昱人
• Other Authors: 張睿達
• Format: Others
• Online Access: http://ndltd.ncl.edu.tw/handle/65188317954118445749

碩士 === 長庚大學 === 電子工程學研究所 === 96 === Three-dimensional device simulation is performed for array devices in dynamic random access memories (DRAM). The doping profile is initially generated by process simulator TSUPREM4. The doping profile is then mapped to device simulator of Sentaurus Device. Different methodologies were tried to optimize the two-dimensional mesh. After that, two-dimensional structure was extended to three-dimensional structure. Simulated curves of device driving current versus applied voltage were used to examine the mesh property. Shallow trench isolation(STI) was incorporated in the three-dimensional simulation. The corner effect of STI was examined by the simulation. Charges in oxide were implemented in our simulation to calibrate the threshold voltage and subthreshold swing for different device dimensions. The resistance for test pattern is also considered for different device geometry.