| Summary: | 碩士 === 長庚大學 === 電子工程研究所 === 96 === In this thesis, a build-in linearizer was used to improve the linearity of power amplifier by using a 0.15μm AlGaAs/InGaAs D-mode pHEMT process. The implementation is based on a cascade architecture that combined a class A and class AB circuitry for 5.2GHz WLAN application.
In Chapter 2, that presents a dual-band Wilkinson power divider operating at two different frequencies by two sections transmission line with different characteristic impedance and parallel connection of a resistor, an inductor, a capacitor. The simulation result shows the return loss is -18.982 dB, insertion loss is -3.365 dB, isolation is -21.368 dB for 2.3GHz and the return loss is -28.274 dB, insertion loss is -3.765 dB isolation is -25.913 dB for 5.8GHz.
In Chapter 3, that presented the basic circuitry topology and used the technology to design a linearity of power amplifier with build-in linearizer. The simulation result exhibits the power gain of 22.766 dB with an output power of 23.548 dBm, gain (S21) of 26.375 dB and power-added efficiency (PAE) is 30.565%.
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